1. Field of the Invention
The present invention is generally directed to multiplexer circuit design. More specifically, the present invention is directed to avoiding contention in one-hot or one-cold multiplexer circuits which can result in abnormal circuit behavior or damage to the circuit.
2. Background
Microprocessor designs typically include multiplexer circuits which permit the selection of one of a number of input signals. Multiplexers are commonly implemented with AND and OR gates as illustrated in FIG. 1. In the simple example of FIG. 1, if the select line 100 is 1 or high, the logic value at xe2x80x9caxe2x80x9d 102 is passed through to the output xe2x80x9ccxe2x80x9d 104, and if the select line 100 is 0 or low, the logic value at xe2x80x9cbxe2x80x9d 106 is passed through to the output xe2x80x9ccxe2x80x9d 104. The problem with such a simple AND/OR multiplexer is that it is slow by virtue of the fact that signals must pass through two levels of gates. It is therefore not used in high-speed microprocessor applications.
High performance microprocessor designs typically contain logic controlled by one-out-of-n input signals, such as an n-to-1 multiplexer implemented with n transmission gates. The high-speed bi-directional transmission gates are each enabled by a different select line. The AND/OR multiplexer of FIG. 1 is implemented as a transmission gate multiplexer as illustrated in FIG. 2. Rather than having just one select line and inverting it as in the AND/OR multiplexer, the transmission gate multiplexer has two select lines which avoids the need for two levels of logic. Referring to FIG. 2, when the select line sell 200 is 0 or low, the logic value at xe2x80x9caxe2x80x9d 202 is passed through to the output xe2x80x9ccxe2x80x9d 204, provided that select line sel2206 is 1 or high so that the logic value at xe2x80x9cbxe2x80x9d 208 is also not passed through. Similarly, when the select line sel2206 is 0 or low, the logic value at xe2x80x9cbxe2x80x9d 208 is passed through to the output xe2x80x9ccxe2x80x9d 204, provided that select line sell 200 is 1 or high so that the logic value at xe2x80x9caxe2x80x9d 202 is also not passed through. It is therefore apparent that the control logic 210 controlling the select lines 200, 206 must be designed to maintain the select lines in a one-cold condition, where only one of the select lines is low logic. That is, the control logic 210 can never permit both sel1200 and sel2206 to be 0 or low simultaneously. Such a condition can result in abnormal circuit behavior and possible circuit damage if the logic values at xe2x80x9caxe2x80x9d 202 and xe2x80x9cbxe2x80x9d 208 are opposite values, such as where a=1 and b=0. This state of contention essentially creates a short circuit from a=1 (supply voltage) to b=0 (ground).
Although the control logic in multiplexer circuits is designed to avoid the problem of contention during normal circuit operation, other circumstances encountered during power-up and testing of the circuit can also create contentious states leading to abnormal circuit behavior and circuit damage. These circumstances are independent of the control logic design. The first circumstance occurs during system power-up where the state of the flip-flops controlling the multiplexer select lines, sel1200 and sel2206 in FIG. 2 for example, is unknown. The potential exists for both sel1200 and sel2206 to be 0 or low simultaneously, creating contention as described above.
The second circumstance which can lead to contention occurs during the testing mode of the multiplexer integrated circuit. During testing and debugging of a circuit design, known inputs should create expected outputs. When anomalous output is encountered, a circuit-testing routine typically stops the system clock and puts the circuit into a scan mode as is well known to those skilled in the art. The scan mode typically configures all the flip-flop registers in the circuit into one large shift register or scan chain. The scan chain is then shifted out, permitting the examination of data from each flip-flop to determine what condition within the circuit is causing the anomalous output. During shift-out of the scan chain, the possibility exists for multiplexer select lines such as sel1200 and sel2206 in FIG. 2 to be in a state which creates a contentious condition as described above.
The transmission gate multiplexer circuit of FIG. 3 more fully illustrates the problem of multiplexer contention during a scan chain shift. In the example circuit of FIG. 3, a 4-to-1 multiplexer structure is designed using four transmission gates. The non-inverting outputs xe2x80x9cqxe2x80x9d of flip-flops FF0, FF1, FF2 and FF3 drive select lines selb0, selb1, selb2 and selb3 respectively. The select lines of the multiplexer are active low (or logic xe2x80x9c0xe2x80x9d), and only one select line should be active at any given time for the multiplexer to function correctly. Under normal operation, this condition is usually ensured by the logic driving the flip-flop inputs. However, during the test mode, when the scan chain is being shifted, there is a possibility that more than one flip-flop output driving the multiplexer select lines will become low at the same time. As illustrated in FIG. 3, select lines selb0300 and selb3302 are both low (or logic xe2x80x9c0xe2x80x9d) at the same time during the scan operation, resulting in a short circuit through transmission gates PS0304 and PS3306 between data input d0=1 308 (supply voltage) and data input d3=0 310 (ground).
A common solution to the potential contention created by shifting the scan chain during test mode or system power-up is illustrated by the circuit of FIG. 4. In the circuit of FIG. 4, three NAND gates ND0, ND1 and ND2, are incorporated into the select lines selb0, selb1 and selb2 respectively. In addition, one NOR gate, NR3, is incorporated into select line selb3. An extra control input tri_en_n, is provided to control these extra gates. In order to compensate for the polarity change of the select lines due to the addition of the extra gates, the inverting outputs xe2x80x9cqbxe2x80x9d of flip-flops FF0, FF1, FF2 and FF3 are used to drive select lines selb0, selb1, selb2 and selb3. During normal operation, the control input tri_en_n is kept at the logic high state. Therefore, the three NAND gates and one NOR gate operate as mere inverting logic, which again, is compensated for by using the inverting outputs xe2x80x9cqbxe2x80x9d of flip-flops, thus maintaining the same logic functionality during normal operation. However, during test mode when shifting the scan chain or at system power-up, the control input tri_en_n is forced to a logic low state which causes the three NAND gate outputs (i.e. selb0, selb1 and selb2) to be a logic high and the NOR gate output (i.e. selb3) to be a logic low. Therefore, the mutual exclusivity or one-cold condition on the multiplexer select lines is satisfied during the scan operation and at system power-up.
Although this is a simple solution, it suffers several disadvantages. The first problem is that of uneven delays in the multiplexer select lines. The delay of the three NAND gates is different than the delay of the one NOR gate. As is known to those skilled in the art, NOR gates have a longer delay than NAND gates by virtue of the differing P-type and N-type parallel and serial transistor configurations which make up NAND and NOR gates. During the time period of this delay difference on the multiplexer select lines, a short circuit can exist such as the one illustrated in FIG. 3 with a path formed through transmission gates PS0304 and PS3306 between data input d0=1 308 (supply voltage) and data input d3=0 310 (ground). Such a condition can cause abnormal circuit behavior and circuit damage. In order to avoid this problem, extra circuit design effort is necessary to ensure that the same delay is seen at the multiplexer select lines through both types of logic gates.
Furthermore, as is known to those skilled in the art, decreased mobility in P-type transistors versus N-type transistors means that P-type transistors are inherently slower than N-type transistors which in turn dictates that P-type transistors in NOR gates are made slightly larger than in NAND gates in order to compensate for the slower P-type transistor configuration in NOR gates. The NOR gate therefore takes up more space than the NAND gate which is a significant consideration as designers strive to decrease circuit size. In addition, the larger size of the NOR gate increases the loading on the NOR gate inputs being driven by the flip-flops, which requires yet further design consideration.
Thus, prior solutions to the problem of a contention resulting from shifting the scan chain during test mode or during system power-up are asymmetrical solutions which have design related problems as well as functional problems. Accordingly, there exists a need for a multiplexer circuit which overcomes disadvantages in the prior art in avoiding contention while maintaining functionality and during operations such as shifting the scan chain in a test mode and during system power-up.
A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes a same-gate symmetrical design and reverse polarity control signals to overcome disadvantages of prior circuits while accommodating increasing circuit speeds. The circuit employs all NAND gates on the select lines controlling multiplexer transmission gates rather than NAND gates and a NOR gate. The design may also be implemented using AND gates. In addition to using a NAND gate where prior designs use a NOR gate, the polarity of the flip-flop output which drives the additional NAND gate is inverted, and the polarity of the input to the transmission gate driven by the additional NAND gate is also inverted. The circuit thus provides a symmetric design using the same NAND logic gates on all select lines while preserving functionality of the n-to-1 multiplexer. The symmetry of the design avoids problems which are inherent to prior asymmetrical designs having NAND gates and a NOR gate, such as uneven delays on the select lines which can result in a short circuit for brief periods of time and the additional design effort required to overcome loading on NOR gate inputs resulting from NOR gates having increased area.